This invention relates to a method of fabrication of a semiconductor integrated circuit device; and, more particularly, the invention relates to a technique applicable effectively to a method of fabrication of a semiconductor integrated circuit device having buried interconnects with copper in the main conductor layers thereof.
In semiconductor integrated circuit devices, electronic devices, etc., a technique has been established to form interconnects as an interconnect-forming technology, wherein a conductor film, e.g., aluminum or tungsten, is deposited on an insulation film, and then the film is patterned by the usual photolithography and dry-etch technique, thereby being formed into an interconnect.
In the above interconnect-forming technique, however, there is a conspicuous increase in interconnect resistance resulting from scale-down of the devices and interconnects forming semiconductor integrated circuit devices or the like, resulting in occurrence of an interconnect delay. Thus, there is a limitation to further improvement in the performance of a semiconductor integrated circuit device or the like. For this reason, in recent years studies have been made on an interconnect-forming technology called “damascene”, for example. The damascene technology can be roughly divided into a single-damascene technique and a dual-damascene technique.
The single damascene technique is a method in which, after forming an interconnect trench in an insulation film, a main conductor layer for interconnect formation is deposited in the interconnect trench; and, then, the main conductor layer is polished so as to be left only at the inside of the interconnect trench, using chemical mechanical polishing (CMP), for example, thereby forming a buried interconnect at the inside of the interconnect trench.
Meanwhile, the dual damascene technique is a method in which, after forming an interconnect trench and a hole for connection to the lower-leveled interconnect in an insulation film, a main conductor layer for interconnect formation is deposited on the insulation film and in the interconnect trench and hole; and, then, the main conductor layer is polished so as to be left only at the inside of the interconnect trench and hole, using CMP or the like, thereby forming a buried interconnect at the inside of the interconnect trench and hole.
In any of the techniques, the interconnect main conductor material comprises, for example, a low-resistance material, such as copper, from a viewpoint of improving the performance of the semiconductor integrated circuit device or the like. Copper, having the advantage of lower resistance and greater allowable current in reliability by two orders of magnitude than that of aluminum, requires a smaller film thickness for the same interconnect resistance, and, hence, results in a reduced capacitance between adjacent interconnects.
However, copper tends to more readily diffuse into an insulation film as compared to other metals, such as aluminum and tungsten. For this reason, it is considered that, when using copper as an interconnect material, there is a need to form a copper-diffusion-preventing thin conductive barrier film on a surface of a copper main-conductor layer (bottom and side surfaces), i.e. on an inner wall of the interconnect trench. Meanwhile, there is a technique in which a cap film, for example, of silicon nitride, is deposited over the entire upper surface of an insulation film formed with an interconnect trench in a manner covering the upper surface of a buried interconnect, thereby preventing copper in the buried interconnect from diffusing into the insulation film through the upper surface of the buried interconnect.
The buried interconnect technology having a copper main-conductor layer is described, for example, in JP-A-11-330246. This technique is such that, after forming a copper interconnect in an interconnect opening formed in a dielectric layer, a barrier layer is formed; and, then, a plasma process is carried out using only ammonia as a source gas, thereby improving the adhesion between the copper interconnect and the copper barrier layer. Meanwhile, JP-A-11-16912, for example, discloses a technique to eliminate an oxide layer formed in an interconnect part exposed at a bottom of a connection hole by carrying out a heat plasma or ultraviolet-ray illumination process in a deoxidizing atmosphere.
Meanwhile, a post-CMP cleaning technique is described, for example, in “Monthly Semiconductor World, published Oct. 1998” Sep. 20, 1998, by Press Journal, pp 62–72.